The invention relates to a configuration for data transmission and a data transmission method. The data is transmitted between a semiconductor memory module set up for this purpose and a memory controller module controlled by a system clock signal.
With increasing rapidity of data transmission in semiconductor memory systems, it has become more difficult to correctly receive the data that is sent from a semiconductor memory module (e.g. DRAM) to a memory controller. This is increasingly difficult above all at very high data transmission frequencies, since the propagation times of the transmitted data signals are longer than the period of the individual data bits.
Nowadays a data strobe signal, as it is known, is used in double data rate (DDR) memory systems. The data strobe signal is an additional signal that, together with the data, is sent from the semiconductor memory module to the memory controller.
By using the data strobe signal, the memory controller is able to detect which phase angle the incoming data has.
The use of the data strobe signal has the disadvantage that the test of the relative time position between the data strobe signal and the data response signal by the memory modules is very time-consuming and costly. Since complicated routines are often needed for this purpose the testing time is increased, which has a detrimental effect on the cost structure. A data strobe signal is normally used for each memory module, which increases the number of pins for the memory connecting plug and therefore, likewise the costs.
It is accordingly an object of the invention to provide a configuration for data transmission in a semiconductor memory system, and a relevant data transmission method, that overcome the above-mentioned disadvantages of the prior art devices and methods of this general type, in which data is transmitted between at least one semiconductor memory module and a memory controller controlled by a system clock signal, in such a way that a data transmission at very high speed is possible and at the same time the disadvantages associated with the use of the data strobe signal can be avoided. A further object of the invention is to specify a data transmission method for a semiconductor memory system of this type which makes possible very fast data transmission between the memory controller and the at least one semiconductor memory module and which avoids the above-described disadvantages of the use of the data strobe signal. Another object of the invention is to specify a memory controller module set up for this data transmission method and a semiconductor memory module set up for this purpose.
With the foregoing and other objects in view there is provided, in accordance with the invention, a configuration for transmitting data in a semiconductor memory system. The configuration contains at least one semiconductor memory module and a memory controller controlled by a system clock signal. The memory controller has a clock generating device producing a sense clock signal in addition to the system clock signal. The data is transmitted between the memory controller and the semiconductor memory module. A clock line is connected between the semiconductor memory module and the memory controller. The clock line transmits the system clock signal to the memory module. At least one separate sense clock line extends from the memory controller to the semiconductor memory module and directly back to the memory controller. The separate sense clock line transmits the sense clock signal to the semiconductor memory module and from the semiconductor memory module back to the memory controller. The memory controller further has a propagation time measuring device connected to the separate sense clock line for measuring a propagation time of the sense clock signal transmitted over the separate sense clock line and a delay time adjusting device connected to the propagation time measuring device. The delay time adjusting device adjusts a delay time corresponding to the propagation time needed by the data transmitted from the semiconductor memory module to the memory controller. The memory controller adjusts the delay time of the delay time adjusting device in accordance with the propagation time, measured by the propagation time measuring device, of the sense clock signal transmitted over the separate sense clock line.
According to a first aspect of the invention, the first part of the object is achieved in that the memory controller has a clock generating device which produces a sense clock signal in addition to the system clock signal. In the memory system, at least one additional sense clock line leads to the memory module and from there directly back to the memory controller, the sense clock line transmitting the sense clock signal to the memory module and from there back to the memory controller. The memory controller further has a propagation time measuring device for measuring the propagation time of the sense clock signal transmitted via the sense clock line and a delay time adjusting device, which are set up to adjust a delay time which corresponds to the propagation time needed by the data transmitted from the respective memory module to the memory controller. The memory controller adjusts the delay time of the delay time adjusting device in accordance with the propagation time, measured by the propagation time measuring device, of the sense clock signal transmitted via the sense clock line.
The inventive step therefore lies in leading an additional clock signal, the sense clock signal, from the memory controller to the semiconductor memory module and back to the memory controller via at least one additional sense clock line in the semiconductor memory system. In the memory controller there is the propagation time measuring device which determines the propagation time of the sense clock signal transmitted via the sense clock line, and the delay adjusting device which is set up to adjust a delay time which corresponds to the propagation time needed by the data transmitted from the respective memory module to the memory controller. The delay time being set in accordance with the propagation time, measured by the propagation time measuring device of the sense clock signal transmitted via the sense clock line. In the event that a plurality of semiconductor memory modules possibly having different specifications are driven by the memory controller, the propagation times of the sense clock signals transmitted via the sense clock lines from the memory controller to the memory modules and from there back to the memory controller are as a rule different. Since the memory controller knows from which memory module it has requested the data, the appropriate delay times for the individual memory modules can be adjusted on the delay adjusting device. A precondition for this is that the propagation time measuring device for measuring the propagation time of the sense clock signals transmitted via the sense clock line are present in the memory controller. The invention is not restricted to two memory modules. More or fewer than two memory modules are possible. Likewise, the scope of the invention includes memory systems in which the memory modules are not accommodated on separate circuit board substrates but, together with the memory controller, on one circuit board substrate. Therefore, the memory modules are then located on the main circuit board, as are the memory controller and the corresponding system clock lines and the additional sense clock lines. In the case of the data transmission according to the invention, it is important that the sense clock lines, which are driven by the memory controller, are looped back directly from the respective memory module to the memory controller without an additional clock module being used on the memory module, such as, for example, a PLL or DLL circuit.
According to one development, however, various passive components such as resistors and/or capacitors and/or inductors can be connected to the sense clock line, for example on the memory module, in order to match the time delay of the sense clock line to the system requirements.
Furthermore, in another development of the invention, the sense clock signal on the sense clock lines can be generated intermittently, that is to say that in a holding state it remains constant and, in the process, assumes a state xe2x80x9clowxe2x80x9d or xe2x80x9chighxe2x80x9d or xe2x80x9cstate of high impedancexe2x80x9d. In this way, the propagation times can be measured again and again. As long as the sense clock line transmits a periodic sense clock signal, it can be used to determine the phase angle of the data in the memory controller.
The clock generating device can generate the sense clock signal at the same or an integer multiple of the frequency of the system clock signal.
According to a further aspect of the invention, a memory controller module for use in a data transmission configuration in a semiconductor system is proposed. Data is transmitted between at least one semiconductor memory module and the memory controller module controlled by a system clock signal. The memory controller module has a clock generating device which generates a sense clock signal which has the same frequency or an integer multiple of the frequency of the system clock signal, a sense clock receiving device for receiving the sense clock signal transmitted via a sense clock line to the memory module and from there back to the memory control module, a propagation time measuring device for measuring a propagation time of the sense clock signal transmitted via the sense clock line and a delay adjusting device, which is set up for the adjustment of a delay time corresponding to the propagation time of the data transmitted from the respective memory module to the memory controller. The delay adjusting device adjusts the delay time in accordance with the propagation time of the received sense clock signal as measured by the propagation time measuring device.
According to a further aspect of the invention, a semiconductor memory module for use in a semiconductor memory system is proposed, in which data is transmitted between the semiconductor memory module and a memory controller controlled by a system clock signal. The semiconductor memory module has terminals and at least one conductor loop for connecting a sense clock line and for looping a sense clock signal generated by the memory controller and transmitted via the sense clock line directly through the semiconductor memory module.
According to a further aspect of the invention, a method for data transmission in a semiconductor memory system is proposed, in which the data is transmitted between at least one semiconductor memory module and a memory controller controlled by a system clock signal. The method includes:
a) generating a sense clock signal in the memory controller in addition to the system clock signal;
b) leading at least one additional sense clock line from the memory controller to the memory module and from there directly back to the memory controller;
c) transmitting the additional sense clock signal via the additional sense clock lines from the memory controller to the memory module and from there back to the memory controller;
d) measuring the propagation time of the sense clock signal transmitted via the sense clock lines in the memory controller;
e) adjusting a delay time corresponding to a L=I propagation time needed by the data from the memory module to the memory controller in accordance with the measured propagation time of the transmitted sense clock signal in the memory controller.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a configuration for data transmission in a semiconductor memory system, and a relevant data transmission method, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.